The invention relates to component ratio determination. More particularly, the invention relates to systems and methods for determining component ratios and the application of correction factors in sampling systems.
Although real world signals are analog, it is often desirable to convert them into the digital domain using analog to digital converters (ADCs). Circuit designers are motivated to perform this conversion because of the efficient methods currently available for the transmission, storage and manipulation of digital signals. A digital representation of an audio signal, for example, allows a CD player to achieve virtually error free storage using optical discs. The need for complicated signal processing may also necessitate analog-to-digital conversion because such signal processing is only feasible in the digital domain using either digital computers or special purpose digital signal processors. Signal processing in the digital domain is also particularly useful in such areas as biomedical applications to provide the required accuracy for such tasks such as magnetic resonance imaging (MRI).
In operation, an analog to digital converter acquires a representative analog signal (a “sample”) and compares that sampled signal to a reference level in order to quantize the sampled signal into the digital domain. For example, a sampled analog input signal may be compared in succession to multiple different voltage levels which are based in part on the reference level. The outcome of these comparisons is used to create a digital word which represents the digital value of the sampled analog signal. Such converters are known in the art as Successive Approximation Register converters (SARs).
One popular type of SAR is the charge redistribution SAR which uses a charge-scaling digital-to-analog converter (DAC) to sum the sampled analog input signal with preset fractions of the reference level. This is typically implemented using an array of individually switched, binary-weighted capacitors which combine to produce the preset fractions of the reference level. The sum of the input signal and the preset fractions of the reference level are successively compared to a preset level (e.g., ground) to produce comparison bits until the resolution limit of the converter is reached.
In order for the ADC described above to operate with the desired precision, its capacitors must be properly proportioned with respect to one another or conversion errors occur. The ADC relies on precise proportioning ratios in order to produce the preset fractions of the reference level with sufficient accuracy to ensure meaningful and accurate conversion of the sampled analog input signal. For example, in many ADCs it is common for comparison capacitors to be connected with one common terminal and arranged in descending order, with each subsequent capacitor having a value of half of the preceding larger capacitor. Each capacitor typically has a unique terminal that is selectively connected to one of two terminals of a reference level source and forms a voltage divider with the other comparison capacitors.
This causes a preset fraction of the reference level to develop on the common terminal of the comparison capacitors, which is summed with the sampled analog input signal. The common terminal of the comparison capacitors is then connected to a comparator which provides a digital output based on the comparison of the summed value to the known value.
Nevertheless, when capacitor values vary due to imprecision associated with manufacturing tolerances, the voltage divider ratios are adversely affected, introducing errors in the preset fractions of the reference level. This, in turn, introduces errors in the digital quantization process.
In view of this known problem, numerous schemes have been proposed that correct this conversion error. One known solution involves the use of trim tables that compensate for errors or “mismatches” in comparison capacitors during the conversion process. This is generally accomplished by providing a trim table that includes compensation values which are added to, or subtracted from, the summed voltage to correct for any errors in the applied fractional reference level due to capacitance mismatch (i.e. to compensate for the incorrect amount of charge provided by the improperly proportioned capacitors).
Such trim tables are populated with values that may be determined during a calibration phase and are based on comparisons of the generated digital representations, which are converted back to analog, with the original sampled analog input signal. This approach requires the use of another dedicated DAC circuit, such as a sub-DAC, that converts the digital trim table entries back to the analog domain for subsequent combination with the summed signal during the conversion process to provide the compensation necessary to correct for capacitor imprecision.
This type of architecture, however, suffers from several drawbacks. For example, the dedicated DAC circuit of these prior art systems are exposed to processing gradients, package stress and other factors which may differ significantly from those of the primary measurement DAC, which may introduce correction factor errors. Additionally, valuable die space must be devoted to the dedicated DAC, which has no purpose other than to perform the calibration function.
Furthermore, in such systems, the application of one or more trim table correction factors occurs during the actual analog to digital conversion process itself. That is, every time a bit is tested against the sampled analog input signal, the dedicated DAC provides charge that adjusts the weight of the bit under test to the desired weight. Thus, the dedicated DAC is perpetually active during the conversion, constantly switching charge in and out for every bit test. This type of calibration during conversion may be referred to as “in-the-loop” calibration.
The constant capacitive switching associated with this in-the-loop calibration approach introduces noise in the system, adversely affecting the analog portions of the circuit, and undesirably imposes a significant switching load on the reference source, both of which may degrade circuit performance.
Thus, in view of the foregoing, it would be desirable to provide systems and methods that overcome these and other drawbacks of the prior art.